Lattice

Mach


MachXO
Designed to remove the complexity of choosing between CPLDs and low-capacity FPGAs – with glue logic, bus bridging, bus interfacing, power-up control, and control logic you no longer need to choose. With up to 271 IOs MachXO are perfect for a wide range of applications that require general purpose I/O expansion, interface bridging and power-up management functions.
Mach
Features
●Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM
●SRAM based logic can be reconfigured in milliseconds using JTAG port
●IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS
●Up to two analog PLLs per device that enable clock multiply, divide and phase shifting
●Available in TQFP, csBGA, caBGA and ftBGA packages

More on MachXO
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