LatticeECP2/M - FPGA

With up to 95 K LUTs and up to 5.3 Mbit block and Distributed RAM the LatticeECP2 and LatticeECP2M families integrate capabilities previously only found on higher cost FPGAs. High jitter tolerant, low transmission SERDES with PCS blocks can be configured to support an array of popular data protocols including PCI Express, Ethernet (1 GbE and SGMII), OBSAI and CPRI.
LatticeECP2/M - FPGA
●Embedded SERDES supports data rates up to 3.125 Gbps (LatticeECP2M only)
●Up to 42 sysDSP™ blocks for high performance multiply and accumulate
●55 Kbits to 5308 Kbits sysMEM™ Embedded Block RAM (EBR)
●sysCLOCK Analog PLLs and DLLs enable clock multiply, divide, phase & delay adjust
●Available in TQFP, PQFP and fpBGA, packages

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