Marvell

Teralynx T100 102.4T Switch

Teralynx T100
102 Tbps Ethernet switch series for AI data center networks
Teralynx T100 102.4T Switch

Product Introduction

As artificial intelligence (AI) workloads continue to grow in complexity and scale, the infrastructure supporting AI models must evolve to meet performance, efficiency, and scalability demands. These complex workloads require massive data transfers between XPUs, CPUs, and storage. A XPU-to-XPU backend network is designed to facilitate high-speed, deterministic low-latency communication between multiple XPUs for parallel processing and intensive computational tasks.

The Marvell® Teralynx® T100 is designed to be Ultra Ethernet Consortium (UEC) compliant, targeting large-scale XPU scale-out networks such as multi-thousand-XPU AI training clusters and rail-optimized backend fabrics. It supports UEC’s Ultra Ethernet Transport (UET) for XPU-to-XPU RDMA, enabling packet spraying and out-of-order packet delivery across multiple parallel paths to maximize link utilization and eliminate flow-level congestion hot spots. Combined with advanced, standards-based congestion control and multi-pathing, the T100 helps ensure consistent low-latency, high-bandwidth performance for collective operations (all-reduce, all-to-all, all-gather) across the largest AI training and inference clusters.

The Teralynx series of Ethernet switch silicon has been architected from the ground up to provide the most optimized Ethernet solutions for AI networks. It offers the industry’s lowest deterministic latency, unmatched visibility through fine-grained telemetry, the industry’s best performance-per-watt power efficiency, large buffers and rich programmability. Teralynx offers a broad range of data center switches with full software/SDK compatibility across the entire series.

Example Use Cases

  • Scale out. Rail-optimized backend fabrics connecting multi-thousand-XPU AI training clusters, enabling UEC-compliant, non-blocking spine and leaf connectivity across large GPU/XPU domains with deterministic low latency and lossless RDMA transport.
  • Scale up. High-radix, low-latency interconnect for tightly-coupled XPU pods and rack-scale domains, supporting dense all-to-all connectivity within a node or rack to maximize collective-operation performance (all-reduce, all-gather, all-to-all) before traffic crosses into the scale-out fabric.  

Key Benefits

Groundbreaking performance and scale enable customers to deploy transformative solutions with reduced power consumption, latency and cost.
  • Innovative 200 Gbps PAM4 SerDes lowers the cost per bit and enables higher scale I/O such as 800GbE and 1600GbE while maintaining backward compatibility with 50G and 100G PAM4.
  • Substantial reduction in power consumption due to monolithic design eliminating the overhead of die-to-die communication.
  • Industry-leading deterministic low latency helps mitigate issues caused by tail latency, reducing job completion times for training and fine-tuning workloads, while simultaneously improving tokenomics – tokens/sec/XPU - the key efficiency metric for inference clusters serving real-time AI applications.
  • Enhanced buffer sharing capability provides robust packet handling in a low entropy, high bandwidth AI network minimizing congestion and latency. The same capability is equally critical for disaggregated inference architectures, where incast traffic patterns emerge between prefill servers, KV-cache tiers, and decode servers, demanding precise buffer management to sustain throughput and response SLAs.
  • Rich and real-time analytics capability with sub second accuracy that can easily integrate with end user applications using REST APIs.
  • Programmable forwarding pipeline enables support of custom and new standard protocols without requiring spins to future-proof the network.
  • 512 radix along with superior 200 Gbps SerDes performance enables large clusters to be designed with passive copper resulting in massive TCO savings.
  • Teralynx switches support standards-based SAI for seamless integration and programmability in high capacity networks.
*Marvell Authorized Distributor
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